Electronic systems generally include at least one printed circuit board (PCB) containing one or more integrated circuit (IC) chips or ICs. ICs typically include input/output (I/O) pins which may be coupled to various interconnects of the PCB. Testing performance of electronic systems which include PCBs and ICs typically requires testing at multiple levels including at the chip level, at the board level, and at the system level. Testing at the board level includes testing interconnects of the PCB. Testing at the system level requires analysis of interconnections between and among the ICs, the PCBs, and other devices both on and off the PCB.
To enhance testability at the board level as well as at the system level, a common design practice at the chip level is to incorporate boundary scan test logic into an IC in accordance with IEEE Standard 1149.1. 1149.1 specifies the function of JTAG logic, which is named for the Joint Test Action Group, for control of boundary scan testing. Two basic elements of an IC are a core logic and the I/O pins. In accordance with 1149.1, boundary scan cells (BSCs) are inserted between the core logic and the I/O pins of the IC. BSCs are typically inserted for all I/O pins of the plurality of ICs on the PCB and may be used to test the integrity of the interconnections between the plurality of ICs.
Each IC may be controlled by boundary scan logic, in accordance with 1149.1, to operate either in a system mode or in a JTAG test mode. In the system mode, system data signals relating to core functions of the IC are passed through the I/O pins to and from devices external to the IC. In the JTAG test mode, test data are provided by the boundary scan chain for the purpose of testing interconnections between the IC and devices external to the IC. The boundary scan logic also provides test control signals which include mode signals, shift signals, clock signals, and update signals, among others, each of which is well known. The shift control signal instructions include a bypass instruction, a sample instruction, and a cross test instruction. The cross test instruction controls BSCs to perform a boundary scan test among the various ICs.
The IC further includes a test data input (TDI) demultiplexer, a test data output (TDO) multiplexer, a bypass register, an instruction register, an identification register, and a test access port (TAP) controller. The TDI demultiplexer includes an input coupled to receive a test data signal from the boundary scan logic which is typically external to the IC. The TDI demultiplexer includes a first output coupled to a TDI input of a first BSC of the plurality of BSCs in the IC. Each of the BSCs includes a TDI input and a TDO output. Each of BSCs is connected serially from a TDO output to a TDI input to propagate test data signals from one BSC to the next BSC in the chain. The TDI demultiplexer further includes a second output coupled to an input of the core logic, a third output coupled to an input of the bypass register; a fourth output coupled to an input of the instruction register; and a fifth output coupled to an input of the identification register.
The TDO multiplexer includes an output which is coupled to provide a test data signal to another IC or to the boundary scan logic. The TDO multiplexer further includes: a first input coupled to a TDO output of a last BSC of the plurality of BSCs in the IC, a second input coupled to an output of the core logic; a third input coupled to an output of the bypass register; a fourth input coupled to an output of the instruction register, and a fifth input coupled to an output of the identification register. The identification register includes inputs coupled to outputs of the TAP controller. The TAP controller includes inputs coupled to receive a TMS signal, a TCK signal, and a TRST signal from the boundary scan logic.
In general, there are three possible I/O structures for an IC including a two-state I/O structure, a three-state I/O structure, and a bi-directional I/O structure. Each of the three I/O structures provides coupling between the core logic and at least one I/O pin. Any or all of the I/O structures may be used in an IC depending on the particular circumstances. The two-state I/O structure includes a two-state output buffer having an input and an output. The input of the two-state output buffer is coupled to a system data output of the core logic. The output of the two-state output buffer is coupled to an I/O pin. The three-state I/O structure includes a three-state output buffer having an input, an output, and a control input. The input of the three-state output buffer is coupled to a system data output of the core logic. The output of the three-state output buffer is coupled to an I/O pin. The control input of the three-state output buffer is coupled to a three-state system control signal output line of the core logic. The bi-directional I/O structure includes a bi-directional buffer. The bi-directional buffer includes an output buffer element having an input, an output, and a control input and an input buffer element having an input and an output. The control input of the output buffer element is coupled to a bi-directional control signal output line of the core logic. The input of the output buffer element is coupled to a system data output of the core logic. The output of the input buffer element is coupled to a system data received input of the core logic. The output of the output buffer element and the input of the input buffer element are coupled together with an I/O pin.
According to conventional methods and apparatus for boundary scan testing, the BSCs are inserted into the I/O structures between the buffers and the core logic. For a two-state output structure, a BSC is inserted between the core logic and the input of the two-state output buffer. For a three-state output structure, a BSC is inserted between the system data output of the core logic and the input of the three-state output buffer. Also, a BSC is inserted between the three-state control signal output line of the core logic and the control input of the three-state output buffer. For a bi-directional output structure, a BSC is inserted between the system control signal output line of the core logic and the bi-directional output buffer. Also, a bi-directional BSC is inserted between the core logic and the bi-directional output buffer.
Turning first to FIG. 1, a detailed logic block diagram of a prior art BSC 10 is shown. The BSC 10 includes a boundary scan mode multiplexer (mode multiplexer) 12; a shift multiplexer 14, a data shift/capture register 16, and an update data register 18. The mode multiplexer 12 and the shift multiplexer 14 each have a system input (0), an update input (1), an output, and a select line. The data shift/capture register 16 and the update data register 18 each have a data input (D), a clock input (CLK), a normal output (Q), and an inverted output (Q bar or not Q).
The BSC 10 includes a system data input (SDI) line for receiving system signals including system data signals and system control signals from the system signal output lines, including the system data signal output lines and the system control signal output lines, of the core logic. If the BSC 10 is used for control purposes, the SDI line may receive a system control signal from the core logic. If the BSC 10 is used for output, the SDI line may receive a system data signal from the core logic. If the BSC 10 is used for an input, the SDI line becomes a system data received input (SDRI) line for receiving signals from the I/O pin through an input buffer. The BSC 10 also includes a system data output (SDO) line for transmitting signals through an output buffer to the I/O pin. If the BSC 10 is used for an input, the SDO line becomes a system data received output (SDRO) line for transmitting signals to the core logic. The SDI line and the SDO line complete the circuit between the core logic and the I/O structure that was bisected by the insertion of the BSC.
For control of the mode of operation by the boundary scan logic and for various test inputs from the boundary scan logic, the BSC 10 further includes a number of JTAG lines. Part or all of these lines taken collectively are sometimes referred to as forming a JTAG bus. The primary JTAG lines are a TDI line which may receive a TDI signal from the boundary scan logic either directly or via another BSC and a TDO line for providing a TDO signal to the boundary scan logic either directly or via another BSC. These two lines are common to all types of BSCs as they are used to form the chain of BSCs. The JTAG lines further include a ShiftDR signal input line, a ClockDR signal input line, an UpdateDR signal input line, and a Mode signal input line. Each line is coupled to receive the corresponding signal from the boundary scan logic. The various lines and circuit elements are coupled to one another as shown.
Turning now to FIG. 2, a detailed logic block diagram of a prior art bi-directional BSC 20 is shown. The bi-directional BSC 20 includes a bi-directional system multiplexer 22, a direction control multiplexer 24, a bi-directional shift control multiplexer 26, a bi-directional data shift/capture register 28, and a bi-directional update data register 30. The bi-directional system multiplexer 22, the direction control multiplexer 24, and the bi-directional shift control multiplexer 26 each have a system input (0), an update input (1), an output, and a select line. The bi-directional data shift/capture register 28 and the bi-directional update data register 30 each have a data input (D), a clock input (CLK), a normal output (Q), and an inverted output (Q bar or not Q).
Since the bi-directional BSC 20 serves both as an output and an input, it includes an SDI line, an SDO line, an SDRI line, and an SDRO line as described above. Similarly, the bi-directional BSC 20 includes a TDI line, a TDO line, a ShiftDR signal input line, a ClockDR signal input line, an UpdateDR signal input line, and a Mode signal input line. In addition, the bi-directional BSC 20 includes a DIRCTL signal input line. Each line is coupled to receive the corresponding signal from the boundary scan logic. The various lines and circuit elements are coupled to one another as shown.
IEEE Standard 1149.1 was first adopted in 1990. It has been widely used and has proved to be very successful. 1149.1 has been amended once to improve it. However, 1149.1 does not address all situations and design practices. One such practice is the inclusion of capacitive coupling in the interconnections between ICs. A capacitor is added either to the connection between the ICs or to one, the other, or both of the I/O pins of the ICs or the PCBs with connectors. The capacitor is designed to reduce noise and block unwanted common mode voltage differences in the interconnection. For discussion, this will be referred to alternatively as either being AC coupled or DC de-coupled.
Turning now to FIG. 3, a block diagram of ten possible combinations of DC and AC coupled interconnections between two devices is shown. The choice of which of the combinations shown that are actually used depends on the circumstances. Because of the capacitor, the value of a signal at the receiving end of the interconnection is no longer the same as the value at the driving end. The result is that conventional 1149.1 testing becomes impractical on AC coupled interconnections. One will note that there are seven possible AC coupled combinations where 1149.1 will not work as compared to only three DC coupled combinations where 1149.1 will work. As the quest for higher signal speeds continues in the future, the use of AC coupling will increase. This becomes especially true with the development of optical communication signals. The consequence will be less and less reliance on conventional 1149.1 testing.
A definite need exists for a boundary scan testing means for AC coupled interconnections that builds on the advantages of conventional 1149.1 testing. Specifically, a need exists for a boundary scan testing means which is capable of testing both DC and AC coupled interconnections. Ideally, such a testing means would be backward compatible, robust, and inexpensive. A primary purpose of the present invention is to solve these needs and provide further, related advantages.